arm-netbook

arm-netbook@lists.phcomp.co.uk

1082 discussions

identification EEPROM: device ID and device tree pages
by Aaron J. Seigo 06 Nov '13

06 Nov '13

hi... Purpose: assuming agreement on the DIDS layout, below is a proposed definition for the two pages we currently know we must have: * a device ID page * a device tree page Goals: To standardize the process of identifying a chassis (or any hardware device, for that matter?) and the components/devices on the chassis which can not be discovered reliably through probing. Proposal: Define two DIDS conforming pages, one for identification information and the other for device tree information, and assign them Page Identifiers (PID). Implementation: Name: Device Identification PID: 0x01 Page data layout: Byte(s) Value ========== ====================== 2 Device type (assigned centrally) 2 Device revision 4 Vendor ID (assigned centrally) 4 Product ID (vendor generated, registered centrally) N Manufacturer cstring N Product cstring N Serial number cstring Name: Device tree PID: 0x02 Page data consists of a standard “dtb” blob as generated by a device tree compiler (dtc) compliant with the Device Tree standard defined at http://devicetree.org -- Aaron J. Seigo

2 3

identification eeprom: data layout
by Aaron J. Seigo 06 Nov '13

06 Nov '13

hi all, i’m going to try this again in a new thread and with hopefully more clarity. i mixed 4 related topics into one email last time and apparently that doesn’t work here, which is fine. i’ll try again and break this into dedicated threads for each so we can (hopefully) discuss each topic without distraction. this email is about the layout of data on the EEPROM. Purpose: Each chassis needs to ship chassis-specific information such as the vendor and device ID on the identification EEPROM. There must be a defined data structure for that information such that a bootloader/OS loaded on any given CPU card can read it out. Goals: * Appropriate for storage on an EEPROM (low overhead) * Appropriate for access via i2c+smbus * Can be use to store heterogeneous data. Already identified are: * Device and vendor ID * Device tree * Reliable, within the first two constraints, it must involve as few hacks as possible and as many reasonable mechanisms for reliable usage * Extensible, allowing for future expansion as necessary Proposal: To create a specification for the “device information data segment” (DIDS) to be referenced by the EOMA68 standard in relation to the data stored on the EOMA68 identification EEPROM. Keeping it separate from the EOMA68 standard: * keeps the EOMA68 spec concise * allows other open hardware implementations to more easily consider adoption Implementation: The DIDS will consist of a single contiguous block of binary data. The IDS will be segmented into variable size pages, and the IDS will be prefaced with a header. Header The header will be 4 bytes in size with the following layout: Byte Size Value ====== === ==== 0x00 2 Capabilities bytes 0x02 1 Checksum byte 0x03 1 Reserved The capabilities bytes are a bitfield. All bits are currently reserved for future usage and may only be assigned in future revisions of the EOMA68 specification. An IDS for this version of the EOMA68 spec must contain the value 0x00 The checksum byte is the CRC-8 result of the IDS. (The CRC-8 algorithm must be referenced from the final specification to avoid any ambiguities.) The final byte is reserved for future use. Pages Other than the header, the remainder of the IDS will be divided into variable length pages. Each page starts with a header with the following format: Byte Size Value ====== === ==== 0x00 2 Page identifier (defined by EOMA68 spec) 0x02 2 Size of page data The page identifier (PID) is used to detect the layout of the data in the page, and all PIDs up to and including 32768 are defined in the DIDS specification. Values above 32768 are reserved. The page data then follows directly after the header. The maximum size of page data is limited by the page size value contained in 2 bytes, or 64k. A page may consist of 0 bytes of data, which may be used in cases where the PID itself is sufficiently informative on its own. The only page layout exception allowed is for the last, or terminal, page. The 0x00 value is used to identify the terminal page, and the remaining 2 bytes are ignored and therefore may contain any values. The terminal page always has page size of zero, regardless of the value stored in the last 2 bytes. Navigating between pages becomes an exercise in reading page headers, seeking to the end of the page (processing the contents along the way if desired) and repeating for the next page until the terminal page is encountered. There is no page index. Variable length pages without an accompanying index means that it is not possible to seek directly to a given page; however given the relatively small size of the IDS, the small number of pages and that the headers allow skipping from page to page this is deemed acceptable. -- Aaron J. Seigo

4 7

[flying squirrel] need quick review of power input for RTC battery on ATSAM4S
by luke.leighton 06 Nov '13

06 Nov '13

this is mainly a question for joe (and anyone else with schematics review experience!) the goal is to provide dual-power for the ATSAM4S. atmel recommend using 2 diodes however the voltage for the IO needs to be above 3.0v in order to run USB, the AXP209 can only output 3.3v max and a diode would suck 0.7v off of that. so i've been advised to use a MOSFET instead, and need to check it's going to work. so here's the schematic that needs checking: * http://hands.com/~lkcl/eoma/kde_tablet/rev3_review/atsam_vddio_power.png * note the diode which provides backup power (from the AXP209 RTC supply) * also i'd like to use the AXP209's "PWROK" signal to control when the ATSAM4S powers up. the datasheet says it's "HIGH" when power is "OK" and it starts off "LOW" when the AXP209 starts up. as the AXP209 PWROK signal is "HIGH" when "OK", that's why i *believe* that the transistor (Q6) is needed, to invert that so that when PWROK is "HIGH", the MOSFET delivers power. greatly appreciated a quick review of that logic. l.

2 5

identification EEPROM: vendor-defined pages
by Aaron J. Seigo 05 Nov '13

05 Nov '13

hi ... 3rd email in this saga, which asks the question: Should the DIDS spec allow for vendor-defined pages? In the proposed DIDS layout, page IDs above 32767 are reserved. The opens the door for vendor specified pages. A maker may wish to define and add non-standard pages to their DIDS for (at least) one of the two following reasons: * the page definition has been proposed to the standard, but is not yet part of the DIDS spec. this allows a maker/vendor to ship a device with that information without being held up by (or worse: *violating*) the specification. * it may be device implementation specific data, and by allowing the additional pages to be included in the DIDS it allows using a single EEPROM chassis design Benefits include: * allowing re-use of pre-existing chassis PCB layouts without needing to adjust them so as to add additional EEPROMs * prevents inappropriate use of mass storage (do we really want to see more “magic” partitioning, such as magic offset values, for mass storage devices?) * conservation (the ecological argument): if there is space on one EEPROM, why use two? With the proposed paged layout, there is zero technical reason why allowing make/vendor-defined pages would be a bad thing. The DIDS spec has 10s of 1000s of page IDs left to use for standard pages and it comfortably allows for vendor pages without making reading/writing of the DIDS any harder or more complex. There is zero cost to the EOMA68 standards or the DIDS layout by allowing maker/vendor-defined pages. Zero. The only reason provided so far is a desire to control vendors. As a maker/vendor, I find that concept utterly repugnant when there are reliable and sensible technology answers. Specifications should standardize and enable, rather than shackle, adopters. -- Aaron J. Seigo

1 0

[flying squirrel] rev 3 preliminary routing nearly done - HELP NEEDED REVIEWING
by luke.leighton 03 Nov '13

03 Nov '13

almost there, just need a last schematics review, the plan is to send the PCB off early next week (2-3 days time). I REALLY NEED HELP here. reviewing schematics and so on. this will be the first board i've done, and it's detailed and complex (but not amazingly hard). phil, nginx/apache appears to be out on hands.com so i'm putting a copy of the schematics here: http://lkcl.net/tablet2.pdf l.

3 10

LCD wiring diagram for EOMA done up
by joem 03 Nov '13

03 Nov '13

Hi, LCD wiring diagrams done up in kicad (and pdf): http://www.gplsquared.com/eoma_boot/eoma_boot.html#working_lcd The script.fex and guide to how to get it working with Ubuntu 13.04 all there as well. Still waiting on 5" display to turn up to do that as well. When I get the MEB2, I fold it into a case and put the LCD on the lid and make a really smart brick sized brickbook (TM) :D One with 18650 batteries and one without. Hurry up Chris!! I ain't got all day waiting on you for your MEB2!!!! There is a brick I have to make and throw at someone.

3 2

[eoma68] power issues
by luke.leighton 02 Nov '13

02 Nov '13

folks, as you saw a couple months back we have an issue with the EOMA68-A20 CPU Card where [without authorisation] some changes were made to the power distribution by the ODM. i still haven't worked out if those changes were/are a blessing or a curse. a reminder of the issue: they connected the ACIN *directly* to VBUS on the USB-OTG input, removing the usual safety and detection features (a SY6280 plus use of some GPIO) which allow programmable (or AXP209-controlled at least) switching between USB-OTG power and 5V input power. i have this sneaking suspicion that the solution might actually be staring me in the face, so wanted to run it by people, see what they thought. what i *believe* the solution is, is to simply move that USB-OTG/5V detection circuitry (in this case a SY6280 plus use of some GPIO) onto the I/O boards, and to effectively treat the EOMA68 5V power "as if" it was a USB-OTG two-way power system. so rather than have in the spec "you must provide 5V power", change that to "you must imagine that the power circuits are identical to what you'd normally have to do for USB-OTG". which, because wits-tech directly connected the bloody USB-OTG power to the ACIN by fusing the pins together at the AXP209 is actually exactly how it is. the advantage of this change (i say change, it's more like being frog-marched unwillingly towards a solution...) is that if people happen to accidentally plug in the CPU Card into a USB-OTG socket and keep it powered up, then a) the CPU Card will survive unplugging and can transition happily from one chassis to another b) as long as it doesn't draw too much current it would be possible to power a portable device *from* the USB-OTG... or at least charge its battery (if it has one) c) i'm sure there's something else... anyway i *think* it's a blessing - it would just have been nice to have been consulted by the ODM, eh? if anyone's got any other suggestions on how to manage USB-OTG power switching it would be very helpful to hear them: i will put them into the EOMA68 spec as implementation guidelines. l.

1 0

Double checking script.fex for eoma68-a20
by Ryan Mullen 01 Nov '13

01 Nov '13

Hi, I am booting an eoma68-a20 using the script.fex (converted to script.bin with sunxi-tools' fex2bin) found here: http://rhombus-tech.net/allwinner/a20/boot/script.fex I have run the instructions found on that page under the subtitle "setup boot instructions for booting directly off of sd/mmc" and all seems well. However, my kernel (linux-sunxi 3.4 with some custom config options) tells me this when booting: [ 1.663649] [mmc-msg] sw_mci_init [ 1.667156] [mmc-msg] get mmc1's IO(det) failed [ 1.671684] [mmc-msg] Not using mmc1 due to script.bin parse failure [ 1.678123] [mmc-msg] MMC host used card: 0x9, boot card: 0x0, io_card 8 [ 1.685471] [mmc-msg] sdc0 set round clock 400000, src 24000000 [ 1.691708] [mmc-msg] sdc0 set ios: clk 0Hz bm OD pm OFF vdd 3.3V width 1 timing LEGACY(SDR12) dt B [ 1.702062] [mmc-msg] sdc0 Probe: base:0xf0034000 irq:64 sg_cpu:ffdfb000(4fc00000) ret 0. [ 1.710382] [mmc-msg] sdc3 set round clock 400000, src 24000000 [ 1.716717] [mmc-msg] sdc3 set ios: clk 0Hz bm OD pm OFF vdd 3.3V width 1 timing LEGACY(SDR12) dt B [ 1.726839] [mmc-msg] sdc3 Probe: base:0xf0036000 irq:67 sg_cpu:ffdfa000(4fc01000) ret 0. After I boot an initrd, there are no /dev/mmcblk0 entries in my dev filesystem. However, I can make it appear if I do the following: echo 1 > /proc/driver/sunxi-mmc.3/insert This causes the card to be registered at /dev/mmcblk0 as expected. Digging deeper, it would seem that the script.fex sets the card-detect mode for mmc0 and mmc1 both to 1, which is CARD_DETECT_BY_GPIO. The failure in the kernel log occurs when the script.bin parser tries to read the "sdc_det" key and doesn't get a valid value describing the GPIO it should be using, I assume. mmc3 doesn't have that problem because script.fex sets the card-detect mode to 4, which is manual mode - this requires me to write a 1 to the control node in the procfs as I experienced. Is the script.fex incomplete? What's going on here? Thanks for any help, Ryan

3 12

Interfacing touch screen to EOMA68-A20
by joem 01 Nov '13

01 Nov '13

Hi, I got me 5 pieces of 4.3" touch screens. It should be same as the lcd described here that is already working: http://gplsquared.com/eoma_boot/eoma_boot.html#working_lcd It has something extra - 4 wires for a touch interface - resistive. The signal pins are marked: 37 XR Touch panel XR 38 YD Touch panelYD 39 XL Touch panel XL 40 YU Touch panel YU They were purchased from Aliexpress - (cheaper when I bought it). http://www.aliexpress.com/item/4-3-inch-KD43G18-40NB-A1-KD43G18-A5-4-3-C430… Any ideas which cheapie chips best to use with EOMA68-A20 to get touch screen operational? I assume it has to be I2C and somehow a bit of driver software will run and convert the I2C signals to mouse movements. Any pointers appreciated.

2 2

BOM of Cubietruck?
by Alexey Eromenko 30 Oct '13

30 Oct '13

SoC Allwinner A20 $8 (I assume only a bit more expensive than last year's A10 at $7) RAM chip $4 per 4 gigabit. (512 MB) x4 = $16. (Dram exchange) Flash 8GB $2 (dram exchange) Gigabit Ethernet PHY $4 (guesstimate based on old data) Intermediate total ($30) Do you happen to know the price of the following: Wifi+BT chip (it seems to have antenna on chip) How much for ports? VGA HDMI TOSLI NK RJ45 2X USB PCB (board itself) headphones audio out MicroSD slot Assembly work $4 ? Cables Package This will give us a very rough gross profit margin of Cubie.

4 3

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

arm-netbook